The present invention relates to asynchronous digital circuit design and in particular to the testing of asynchronous circuits and systems.
The ever increasing demand for simultaneously faster and more complex digital circuits, e.g., microprocessors, has pushed conventional digital circuit design methodologies to their limits. Because of the combination of high clock rates (i.e., greater than 100 MHz) and design complexity (e.g., very large scale integration (VLSI) devices with 10 million or more transistors), signal propagation delay has become a dominant design consideration. It has become clear that a significant design paradigm shift will be necessary if digital circuit design is to continue its historical adherence to Moore's law.
Asynchronous VLSI is an active area of research and development in digital circuit design. It refers to all forms of digital circuit design in which there is no global clock synchronization signal. Delay-insensitive asynchronous designs, by their very nature are insensitive to the signal propagation delays which have become the single greatest obstacle to the advancement of traditional design paradigms. That is, delay-insensitive circuit design maintains the property that any transition in the digital circuit could have an unbounded delay and the circuit will still behave correctly. The circuits enforce sequencing but not absolute timing. This design style avoids design and verification difficulties that arise from timing assumptions, glitches, or race conditions.
Generally speaking, synchronous design styles are facing serious performance limitations. Certain asynchronous design methodologies also have difficulties with some of the same types of limitations, e.g., race conditions. By contrast, the delay-insensitive branch of asynchronous digital design, because of its relative immunity to these limitations, appears to hold great promise for supporting future advancements in the performance of digital circuits.
However, even if such asynchronous digital design techniques are to be the digital design methodology which enables the performance of digital circuits and systems to continue to improve in accordance with historical norms, the testing of such circuits will likely need to be done using synchronous test equipment for some time to come. That is, virtually all of the commercially available and currently installed base of test equipment is synchronous in nature. As is well known, such test equipment is employed with a variety of standard interfaces, e.g., JTAG and scan interfaces, to facilitate access to (via boundary scans) and verification of synchronous circuit designs using, for example, one or more scan chains.
Because asynchronous designs do not typically employ clock signals, the application of test vectors and the reading of results using conventional synchronous test equipment is not straightforward. It is therefore desirable to provide circuits and techniques for facilitating test access to the internal signal nodes of asynchronous designs using conventional synchronous test equipment.